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International Journal of Applied Research
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ISSN Print: 2394-7500, ISSN Online: 2394-5869, CODEN: IJARPF

Impact Factor: RJIF 5.2

International Journal of Applied Research

Vol. 1, Issue 5, Part A (2015)

Simulation of low power 9 Tfull adder with reduced ground bounce noise technology

Author(s)
M. Lasya, L.M.L Narayana Reddy
Abstract
Low power has emerged as a principal theme in today’s world of electronics industries. Power dissipation has become an important consideration as performance and area for VLSI Chip design. With shrinking technology reducing power consumption and over all power management on chip are the key challenges below 100nm due to increased complexity. For many designs, optimization of power is important as timing due to the need to reduce package cost and extended battery life. For power management leakage current also plays an important role in low power VLSI designs. Leakage current is becoming an increasingly important fraction of the total power dissipation of integrated circuits. An adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. Recently there have been several attempts to design energy recovering logic in the pursuit of energy efficient circuitry. In this paper we are going to design aultra low power 14 Transistor adder using the novel stacking power gating logic which has very low leakage power .
Pages: 05-11  |  634 Views  5 Downloads
How to cite this article:
M. Lasya, L.M.L Narayana Reddy. Simulation of low power 9 Tfull adder with reduced ground bounce noise technology. International Journal of Applied Research. 2015; 1(5): 05-11.
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