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ISSN Print: 2394-7500, ISSN Online: 2394-5869, CODEN: IJARPF

Impact Factor: RJIF 5.2

International Journal of Applied Research

Vol. 1, Issue 7, Part E (2015)

High speed Vedic multiplier design and implementation on FPGA

Author(s)
Prashant D. Pawale, Venkat N Ghodke
Abstract
In high speed digital signal processing units arithmetic logic units, multiplier and accumulate units, thernmultipliers are use as the key block. By increasing constraints on delay, more and more emphasis isrnbeing laid on design of faster multiplications. For high speed applications, a huge number of adders orrncompressors are to be used in multiplications to perform the partial product addition. The Arrayrnmultiplier, Vedic 4*4 multiplier and 8*8 multiplier are designed, then 16*16 multiplier. These addersrnare called compressors. Amongst these Vedic multipliers based on Vedic mathematics are presentlyrnunder focus due to these being one of the fastest and low power multiplier. There are total sixteenrnsutras in Vedic multiplication in that the 14 number which is nothing but “Urdhva Tiryakbhyam” whichrnis nothing but vertically and crosswise to be the most efficient one in terms of speed. Few of them arernpresented in this paper giving an insight into their methodology, merits and demerits. Compressorrnbased Vedic Multipliers show considerable improvements in speed and area efficiency.
Pages: 239-244  |  679 Views  19 Downloads
How to cite this article:
Prashant D. Pawale, Venkat N Ghodke. High speed Vedic multiplier design and implementation on FPGA. International Journal of Applied Research. 2015; 1(7): 239-244.
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