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International Journal of Applied Research
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ISSN Print: 2394-7500, ISSN Online: 2394-5869, CODEN: IJARPF

Impact Factor: RJIF 5.2

International Journal of Applied Research

Vol. 2, Issue 1, Part L (2016)

Implementation of fault tolerant soft processor on FPGA

Author(s)
Sonal Sarode, AS Patil
Abstract
This paper presents design of fault tolerant soft processor and implementation of it on FPGAs. Due to configurability feature and increasingly complex architecture of Field Programmable Gate Arrays (FPGAs) have brought advantages to many applications such as avionics applications and safety critical aerospace. These features of FPGAs allows in system reconfiguration after launch. To enhance FPGAs functionality embedded processors, either soft cores using reconfiguration logic of FPGA or built in hard cores on Xilinx FPGAs, have been up taken in many applications due to close compatibility with high level applications and their flexibility. The most commercial FPGAs suffer from radiation induced faults, which are provoked by high energy particles in space. To harden the fault tolerance of soft processor technique used is Error-correcting code technique. This technique is used especially for memories of soft processors. Error-correcting code technique is demonstrated in implementation of a fault tolerant soft processor on Xilinx FPGAs. In additional we used Look Ahead technique to synchronize Error-correcting code-protected Block Read Access Memory (ECC BRAM) with the soft processor. Without halting the processor, the resulting fault tolerant soft processor has benefit to self recover the memory in presence of Single Error Upsets.
Pages: 781-784  |  580 Views  12 Downloads
How to cite this article:
Sonal Sarode, AS Patil. Implementation of fault tolerant soft processor on FPGA. International Journal of Applied Research. 2016; 2(1): 781-784.
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