Vol. 2, Issue 5, Part E (2016)

Abstract
This paper deals with the study of dependence of Static Noise Margin of SRAM on supply voltage and circuit topologies. Computation of Static Noise Margin of conventional 6T SRAM cell using butterfly curve and its corresponding read & writes operation where explained. This paper also investigates the effects of supply voltage, temperature & sizing of the transistors on SRAM performance. The results of SNM for various topologies and modifications in topologies for improving the performance in the subthreshold region and increasing the speed of the SRAM cell were discussed.