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International Journal of Applied Research
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ISSN Print: 2394-7500, ISSN Online: 2394-5869, CODEN: IJARPF

Impact Factor: RJIF 8.4

International Journal of Applied Research

Vol. 2, Issue 4, Part K (2016)

Review paper on design and implementation of FFT processor using memory based pipelined architecture

Author(s)
Madhavi Naktode, Priti S Chimankar
Abstract
The Fast Fourier Transform (FFT) is an efficient algorithm for computing the Discrete Fourier Transform (DFT) and requires less number of computations than that of direct evaluation of DFT. It has several applications in signal processing. Because of the complexity of the processing algorithm of FFT, recently various FFT algorithms have been proposed to meet real-time processing requirements and to reduce hardware complexity over the last decades. This work presents combined pipelined architecture with memory based architecture to get an area and time efficient architecture that could be used as a coprocessor with built in all resources necessary for an embedded DSP application. The design simulation and its FPGA based implementation have to be verified using Xilinx ISE 14.1 tool using VHDL.
Pages: 677-679  |  667 Views  23 Downloads
How to cite this article:
Madhavi Naktode, Priti S Chimankar. Review paper on design and implementation of FFT processor using memory based pipelined architecture. International Journal of Applied Research. 2016; 2(4): 677-679.
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